Two hardware implementations of the exhaustive synthetic AER generation method
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
IEEE Transactions on Neural Networks
Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip
IEEE Transactions on Neural Networks
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
IEEE Transactions on Neural Networks
On the designing of spikes band-pass filters for FPGA
ICANN'11 Proceedings of the 21st international conference on Artificial neural networks - Volume Part II
A FPGA spike-based robot controlled with neuro-inspired VITE
IWANN'13 Proceedings of the 12th international conference on Artificial Neural Networks: advances in computational intelligence - Volume Part I
Hi-index | 0.00 |
In this paper we will explain in depth how we have used Simulink with the addition of Xilinx System Generation to design a simulation framework for testing and analyzing neuro-inspired elements for spikes rate coded signals processing. Those elements have been designed as building blocks, which represent spikes processing primitives, combining them we have designed more complex blocks, which behaves like analog frequency filter using digital circuits. This kind of computation performs a massively parallel processing without complex hardware units. Spikes processing building blocks have been written in VHDL to be implemented for FPGA. Xilinx System Generator allows co-simulating VHDL entities together with Simulink components, providing an easy interface for presented building block simulations and analysis.