Are hardware performance counters a cost effective way for integrity checking of programs

  • Authors:
  • Corey Malone;Mohamed Zahran;Ramesh Karri

  • Affiliations:
  • Polytechnic Institute of New York University, Brooklyn, NY, USA;Polytechnic Institute of New York University, Brooklyn, NY, USA;Polytechnic Institute of New York University, Brooklyn, NY, USA

  • Venue:
  • Proceedings of the sixth ACM workshop on Scalable trusted computing
  • Year:
  • 2011

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, we propose to use hardware performance counters (HPC) to detect malicious program modifications at load time (static) and at runtime (dynamic). HPC have been used for program characterization and testing, system testing and performance evaluation, and as side channels. We propose to use HPCs for static and dynamic integrity checking of programs.. The main advantage of HPC-based integrity checking is that it is almost free in terms of hardware cost; HPCs are built into almost all processors. The runtime performance overhead is minimal because we use the operating system for integrity checking, which is called anyway for process scheduling and other interrupts. Our preliminary results confirm that HPC very efficiently detect program modifications with very low cost.