Software engineering (5th ed.)
Software engineering (5th ed.)
Structured Computer Organization
Structured Computer Organization
Hierarchical Hybrid Modeling of Embedded Systems
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Proceedings of the 23rd annual international conference on Design of communication: documenting & designing for pervasive information
From UML/SysML to Matlab/Simulink: current state and future perspectives
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A model-driven design environment for embedded systems
Proceedings of the 43rd annual Design Automation Conference
Time Petri Nets Analysis with TINA
QEST '06 Proceedings of the 3rd international conference on the Quantitative Evaluation of Systems
Model-Driven Software Development: Technology, Engineering, Management
Model-Driven Software Development: Technology, Engineering, Management
Applying a Model-based Approach for Embedded System Development
EUROMICRO '07 Proceedings of the 33rd EUROMICRO Conference on Software Engineering and Advanced Applications
A Model-Driven Design Framework for Massively Parallel Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
HiLeS-T: an ADL for early requirement verification of embedded systems
Proceedings of the 5th International Workshop on Model Based Architecting and Construction of Embedded Systems
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Embedded system virtual prototyping allows exploration of solutions in system architecture and hardware specification, prior to real prototype construction, resulting in higher quality products, shorter time to market and cost reduction. Virtual prototypes allow simulation of the system so designers can analyze and evaluate their design decisions against system response. However, benefits in costs, shorter developing times and simulation capabilities can be affected by Virtual Prototype (VP) construction and modification, especially if done directly in Hardware Description Languages (HDL). The reasons are associated with being a manual error prone activity, the difficulty on keeping the VP in conformance to design requirements and the risk of simulations being hard to analyze. We propose a Model-Driven approach to generate automatically from a SysML high-level specification, structure and behavior, a VP in a HDL. Our proposal aims at providing a design methodology, significantly reducing the amount of manual code to diminish errors and increase simulation to design traceability. In our approach, we use a pivot language called HiLeS which is based on a Petri Net formalism facilitating the transformation into the HDL and allowing behavior verification. The paper presents the methodology and the model transformations done, specifically, to obtain from SysML sequence diagrams Petri Net models.