Constructing DEVS models based on experts' knowledge: application to STMicroelectronics' large scale manufacturing processes (Work-in-Progress)

Authors:
Pamela Viale;Claudia Frydman;Jacques Pinaton
Affiliations:
Laboratoire des Sciences de l'Information et des Systémes (LSIS), Marseille, France and STMicroelectronics, Rousset, France;Laboratoire des Sciences de l'Information et des Systémes (LSIS), Marseille, France;STMicroelectronics, Rousset, France
Venue:
Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium
Year:
2011

Citing 1
Cited 1

From sequential machines to DEVS formalism

SCSC '09 Proceedings of the 2009 Summer Computer Simulation Conference

Validating manufacturing processes using timed sequential machines: application to a semiconductor manufacturing process (WIP)

Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium

Quantified Score

Hi-index	0.00

Visualization

Abstract

STMicroelectronics has a spirit of innovation in the development of chips, continuously modifying its production processes for improving performance. This is why it is interested in creating 'generic models' of their manufacturing processes and keeping them updated in spite of the high number of modifications demanded. It is specially interested in capitalizing experts' knowledge. In this article we explain ideas for constructing models for STMicroelectronics manufacturing processes using experts' definitions. The importance of our approach resides in the construction of models that constitute a step forwards to the implementation of an alarm control system over processes modifications.