CORDIC instructions for LDPC decoding on SDR platforms
Analog Integrated Circuits and Signal Processing
Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures
Journal of Signal Processing Systems
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Emerging wireless applications consistently demand higher data rates, but it is challenging to achieve high data rates within the limited amount of available frequency spectrum. Hence, current and future generation wireless protocols require compute-intensive signal processing techniques to increase spectral efficiency and link reliability. Physical layers of compute-intensive wireless protocols traditionally have been implemented using Application Specific Integrated Circuits (ASICs) trading off flexibility for performance. To cope with the increased system complexity and shorter time-to-market, there is a paradigm shift in the wireless market from ASIC solutions to fully programmable Software Defined Radio (SDR) solutions. In many cases, the computational requirements of complicated signal processing techniques cannot be achieved within the communication system's real-time constraints using traditional SDR processors. Hence, novel instructions, hardware designs, and algorithm enhancements are needed to support emerging wireless communication protocols. For this dissertation, compute-intensive algorithms in current and future generation wireless protocols are identified through profiling. It is observed that the kernel operations that utilize majority of the computation time in most of these wireless algorithms involve transcendental functions, vector rotations, and division. The CoOrdinate Rotation Digital Computer (CORDIC) algorithm provides convenient mechanisms to perform these kernel operations. However, the sequential CORDIC algorithm is inefficient to implement completely in software using conventional SDR processors. Hence, this dissertation investigates processor support for the CORDIC algorithm in the context of SDR processors. Multithreading is utilized to improve throughput and hide the latency of the CORDIC instructions.The dissertation presents different ways to map the CORDIC algorithm to a programmable SDR processor and analyzes the associated trade-offs. It provides a comprehensive study of the performance, power, and precision impact of the proposed CORDIC instructions on compute-intensive wireless algorithms when added to the Sandbridge Sandblaster 3000 (SB3000), a state-of-art SDR platform. In particular, when using CORDIC instructions, performance speedups in excess of 4x and power savings from 30% to 66% are observed for the wireless algorithms investigated in this dissertation, at the expense of a new SIMD CORDIC functional unit added to the processor datapath. The CORDIC algorithms also simplify the implementations of the kernel functions in software, reducing programming effort and thus time-to-market. The performance impact of the proposed CORDIC instructions are evaluated on the Long Term Evolution (LTE) Advanced receiver, a large—scale wireless protocol prototype with strict real-time constraints. It is anticipated that the kernel operations for which the CORDIC algorithm demonstrates dramatic speedups and improved power savings will continue to be used in future generation wireless algorithms.