An efficient architectural design of hardware interface for heterogeneous multi-core system

Authors:
Xiongli Gu;Jie Yang;Xiamin Wu;Chunming Huang;Peng Liu
Affiliations:
Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China;Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China;Department of Information Science and Electronic Engineering, UTStarcom Co.Ltd., Hangzhou, China;Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China;Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China
Venue:
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
Year:
2011

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Abstract

How to manage the message passing among inter processor cores with lower overhead is a great challenge when the multi-core system is the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. Generally speaking, the networks-on-chip connects the distributed multi-core system. It takes charge of message passing which including data and synchronization message among cores. The size of most data transmission is typically large enough that it remains strongly bandwidth-bound. The synchronization message is very small which is primarily latency bound. Thus the separated networks-on-chip are needed to transmit the above two types of message. In this paper we focus on the network for the transmission of synchronization messages. A hardware module - message passing unit (MPU) is proposed to manage the synchronization message passing for the heterogeneous multi-core system. Compared with the original single network approach, this solution reduces the run-time object scheduling and synchronization overhead effectively, thereby, improving the whole system performance.