Massively parallel identification of intersection points for GPGPU ray tracing

Authors:
Alexandre S. Nery;Nadia Nedjah;Felipe M. G. França;Lech Jozwiak
Affiliations:
Computer Architecture and Microeletronics Laboratory, COPPE, Universidade Federal do Rio de Janeiro and Department of Electrical Engineering - Electronic Systems, Eindhoven University of Technolog ...;Department of Electronics Engineering and Telecommunications, Universidade do Estado do Rio de Janeiro;Computer Architecture and Microeletronics Laboratory, COPPE, Universidade Federal do Rio de Janeiro;Department of Electrical Engineering - Electronic Systems, Eindhoven University of Technology, The Netherlands
Venue:
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Year:
2011

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Abstract

The latest advancements in computer graphics architectures, as the replacement of some fixed stages of the pipeline for programmable stages (shaders), have been enabling the development of parallel general purpose applications on massively parallel graphics architectures (Streaming Processors). For years the graphics processing unit (GPU) is being optimized for increasingly high throughput of massively parallel floating-point computations. However, only the applications that exhibit Data Level parallelism can achieve substantial acceleration in such architectures. In this paper we present a parallel implementation of the GridRT architecture for GPGPU ray tracing. Such architecture can expose two levels of parallelism in ray tracing: parallel ray processing and parallel intersection tests, respectively. We also present a traditional parallel implementation of ray tracing in GPGPU, for comparison against the GridRT-GPGPU implementation.