A cache-partitioning aware replacement policy for chip multiprocessors

Authors:
Haakon Dybdahl;Per Stenström;Lasse Natvig
Affiliations:
Dept. of Computer and Information Science, Norwegian University of Science and Technology, Trondheim, Norway;Dept. of Computer Engineering, Dept. of Computer Engineering, Chalmers University of Technology, Goteborg, Sweden;Dept. of Computer and Information Science, Norwegian University of Science and Technology, Trondheim, Norway
Venue:
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Year:
2006

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Abstract

Chip multiprocessors (CMPs) usually employ shared, last-level caches to use on-chip memory resources effectively. Unfortunately, conventional replacement policies applied to shared caches fail to partition memory resources among cores to achieve an optimal execution throughput. This paper presents a novel replacement policy that dynamically estimates how many misses would be eliminated if one more block per set would be allocated to a certain processor taking into account the extra misses for some other processor. Our implementation makes novel use of shadow tags for the estimation. We show that it can yield 50% higher execution throughput on a 4-way CMP and in contrast to previously proposed schemes, we did not observe any noticeable degradation of performance for any application in the SPEC2000 we used.