Optimal Partitioning of Cache Memory
IEEE Transactions on Computers
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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Dynamic Partitioning of Shared Cache Memory
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PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
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SkipCache: miss-rate aware cache management
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Managing shared last-level cache in a heterogeneous multicore processor
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Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the multiple cores. Cache partitioning is an effective method for isolating poorly-interacting threads from each other, but designing a mechanism with simple logic and low area overhead will be important for incorporating such schemes in future embedded multi-core processors. In this work, we identify that major performance problems only arise when one or more “thrashing” applications exist. We propose a simple yet effective Thrasher Caging (TC) cache management scheme that specifically targets these thrashing applications.