Functional unit chaining: a runtime adaptive architecture for reducing bypass delays

Authors:
Lih Wen Koh;Oliver Diessel
Affiliations:
Embedded, Real-Time, and Operating Systems (ERTOS) Program, National ICT Australia, School of Computer Science & Engineering, The University of New South Wales, Sydney, Australia;Embedded, Real-Time, and Operating Systems (ERTOS) Program, National ICT Australia, School of Computer Science & Engineering, The University of New South Wales, Sydney, Australia
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affect the performance of sequential code sequences. We propose dealing with these delays through a dynamic functional unit chaining approach. We study the performance benefits of a superscalar, out-of-order processor augmented with a two-by-two array of ALUs interconnected by a fast, partial bypass network. An online profiler guides the automatic configuration of the network to accelerate specific patterns of dependent instructions. A detailed study of benchmark simulations demonstrates these first steps towards mapping binaries to a small coarse-grained array at runtime can improve instruction throughput by over 18% and 25% when the microarchitecure includes bypass delays of one cycle and two cycles, respectively.