Architecture of RETE network hardware accelerator for real-time context-aware system

Authors:
Seung Wook Lee;Jong Tae Kim;Hongmoon Wang;Dae Jin Bae;Keon Myung Lee;Jee Hyung Lee;Jae Wook Jeon
Affiliations:
School of Information and Communication Engineering, Sungkyunkwan University, Korea;School of Information and Communication Engineering, Sungkyunkwan University, Korea;School of Information and Communication Engineering, Sungkyunkwan University, Korea;School of Information and Communication Engineering, Sungkyunkwan University, Korea;School of Electrical and Computer Engineering, Chungbuk National University, Korea;School of Information and Communication Engineering, Sungkyunkwan University, Korea;School of Information and Communication Engineering, Sungkyunkwan University, Korea
Venue:
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Year:
2006

Citing 3
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Abstract

Context-aware systems, such as intelligent home-care systems or mobile communication devices that are aware of the channel environment, need reasoning ability with numerous rules to manage the current context. Reasoning techniques based on rule-based systems can be used for the efficient reasoning method of these numerous rules. The RETE algorithm has been used for the matching of reasoning rules in rule-based systems. However, the characteristics of the RETE algorithm cause it to have poor performance in Von Neumann computer systems. In this paper, we propose a novel architecture for the RETE network hardware accelerator, which provides efficient reasoning processing performance. Using the parallel RETE network hardware architecture, this accelerator can overcome the architectural constraints imposed by Von Neumann computer systems.