AEGIS: architecture for tamper-evident and tamper-resistant processing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Caches and Hash Trees for Efficient Memory Integrity Verification
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
The IBM PCIXCC: a new cryptographic coprocessor for the IBM eServer
IBM Journal of Research and Development
A combined hardware and software architecture for secure computing
Proceedings of the 2nd conference on Computing frontiers
An operating system design for the security architecture for microprocessors
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
A new encryption and hashing scheme for the security architecture for microprocessors
CMS'06 Proceedings of the 10th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
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Protecting software and data becomes more and more important, especially, when sensitive or expensive software is executed on remote hosts. This protection includes copy protection, prevention of disassembling, prevention of altering the program flow and protection of processed data. For personal computers protection is more focused on copy protection. However, providing extended security to prevent data and algorithm disclosure is very important to increase the acceptance for GRID computing. In this paper we present a cache design for a secure combined hardware and software architecture called SAM. For SAM, the cache provides transparent encryption/decryption and content verification using hash values. Additionally, the cache has to consider different memory views and protection levels as well as support for protected shared memory, a key feature of SAM.