Embedding a high speed interval type-2 fuzzy controller for a real plant into an FPGA

  • Authors:

  • Roberto Sepúlveda;Oscar Montiel;Oscar Castillo;Patricia Melin

  • Affiliations:

  • Instituto Politécnico Nacional - CITEDI. Av. del Parque No. 1310, Mesa de Otay, 22510 Tijuana, B.C., Mexico;Instituto Politécnico Nacional - CITEDI. Av. del Parque No. 1310, Mesa de Otay, 22510 Tijuana, B.C., Mexico;Department of Computing Science, Tijuana Institute of Technology, P.O. Box 4207, Chula Vista, CA 91909, USA;Department of Computing Science, Tijuana Institute of Technology, P.O. Box 4207, Chula Vista, CA 91909, USA

  • Venue:
  • Applied Soft Computing
  • Year:
  • 2012

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Abstract

The main goal of this paper is to show that interval type-2 fuzzy inference systems (IT2 FIS) can be used in applications that require high speed processing. This is an important issue since the use of IT2 FIS still being controversial for several reasons, one of the most important is related to the resulting shocking increase in computational complexity that type reducers, like the Karnik-Mendel (KM) iterative method, can cause even for small systems. Hence, comparing our results against a typical implementation of a IT2 FIS using a high level language implemented into a computer, we show that using a hardware implementation the the whole IT2 FIS (fuzzification, inference engine, type reducer and defuzzification) last only four clock cycles; a speed up of nearly 225,000 and 450,000 can be obtained for the Spartan 3 and Virtex 5 Field Programmable Gate Arrays (FPGAs), respectively. This proposal is suitable to be implemented in pipeline, so the complete IT2 process can be obtained in just one clock cycle with the consequently gain in speed of 900,000 and 2,400,000 for the aforementioned FPGAs. This paper also shows that the iterative KM method can be efficient if it is adequately implemented using the appropriate combination of hardware and software. Comparative experiments of control surfaces, and time response in the control of a real plant using the IT2 FIS implemented into a computer against the IT2 FIS into an FPGA are shown.