Hardware architecture and FPGA implementation of a type-2 fuzzy system

  • Authors:
  • Miguel A. Melgarejo, R.;Carlos A. Peña-Reyes

  • Affiliations:
  • Universidad Distrital FJC, Bogota D.C, Colombia;Swiss Federal Institute of Technology at Lausanne, EPFL, Lausanne, Switzerland

  • Venue:
  • Proceedings of the 14th ACM Great Lakes symposium on VLSI
  • Year:
  • 2004

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Abstract

This paper presents an architectural proposal for a hardware-based interval type-2 fuzzy inference system. First, it presents a computational model which considers parallel inference processing and type reduction based on computing inner and outer bound sets. Taking into account this model, we conceived a hardware architecture with several pipeline stages for full parallel execution of type-2 fuzzy inferences. The architectural proposal is used for specifying a type-2 fuzzy processor with reconfigurable rule base, which is implemented over FPGA technology. Implementation results show that this processor performs more than 30 millions of type-2 fuzzy inferences per second.