Memory-centric security architecture

  • Authors:

  • Weidong Shi;Chenghuai Lu;Hsien-Hsin S. Lee

  • Affiliations:

  • College of Computing, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;College of Computing, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;College of Computing, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA

  • Venue:
  • HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
  • Year:
  • 2005

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Abstract

This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for the same purpose, the new architecture ties cryptographic properties and security attributes to memory instead of each individual user process. The advantages of such a memory centric design are many folds. First, it provides a better security model and access control on software privacy that supports both selective and mixed tamper resistant protection on software components from heterogeneous sources. Second, the new model supports and facilities tamper resistant secure information sharing in an open software system where both data and code components could be shared by different user processes. Third, the proposed security model and secure processor design allow software components protected with different security policies to inter-operate within the same memory space efficiently. Our new architectural support requires small silicon resources and its performance impact is minimal based on our experimental results using commercial MS Windows workloads and cycle based out-of-order processor simulation.