Generalized trellis stereo matching with systolic array

Authors:
Hong Jeong;Sungchan Park
Affiliations:
Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, South Korea;Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, South Korea
Venue:
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Year:
2004

Citing 2
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Abstract

We present here a real time stereo matching chip which is based on a general trellis form with vergent optical axis. The architecture can deal with general axis angle of cameras with better resolution in given space. For a pair of images with M × N pixels, only $\mathcal{O}(MN)$ time is required. The design is highly scalable and fully exploits the concurrent and configurable nature of the algorithm. We implement stereo chip on Xilix FPGA with 208 PEs(Processing Elements) that can obtain disparity range of 208 levels. It can provide the real-time stereo matching for the mega-pixel images.