Analysis of a class of communicating finite state machines
Acta Informatica
Theoretical Computer Science
Unreliable channels are easier to verify than perfect channels
Information and Computation
Undecidable verification problems for programs with unreliable channels
Information and Computation
Verifying identical communicating processes is undecidable
Theoretical Computer Science
On Communicating Finite-State Machines
Journal of the ACM (JACM)
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Well-abstracted transition systems: application to FIFO automata
Information and Computation
Verification of programs with half-duplex communication
Information and Computation
On sampled semantics of timed systems
FSTTCS '05 Proceedings of the 25th international conference on Foundations of Software Technology and Theoretical Computer Science
A kleene theorem for a class of communicating automata with effective algorithms
DLT'04 Proceedings of the 8th international conference on Developments in Language Theory
Automata and logics for timed message sequence charts
FSTTCS'07 Proceedings of the 27th international conference on Foundations of software technology and theoretical computer science
Matching scenarios with timing constraints
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Reachability of communicating timed processes
FOSSACS'13 Proceedings of the 16th international conference on Foundations of Software Science and Computation Structures
Event clock message passing automata: a logical characterization and an emptiness checking algorithm
Formal Methods in System Design
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We study channel systems whose behaviour (sending and receiving messages via unbounded FIFO channels) must follow given timing constraints specifying the execution speeds of the local components. We propose Communicating Timed Automata (CTA) to model such systems. The goal is to study the borderline between decidable and undecidable classes of channel systems in the timed setting. Our technical results include: (1) CTA with one channel without shared states in the form (A1,A2, c1,2) is equivalent to one-counter machine, implying that verification problems such as checking state reachability and channel boundedness are decidable, and (2) CTA with two channels without sharing states in the form (A1,A2,A3, c1,2,c2,3) has the power of Turing machines. Note that in the untimed setting, these systems are no more expressive than finite state machines. This shows that the capability of synchronizing on time makes it substantially more difficult to verify channel systems.