Theoretical Computer Science
Event-clock automata: a determinizable class of timed automata
Theoretical Computer Science
On Communicating Finite-State Machines
Journal of the ACM (JACM)
Timing Constraints in Message Sequence Chart Specifications
FORTE X / PSTV XVII '97 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE X) and Protocol Specification, Testing and Verification (PSTV XVII)
An Analyser for Mesage Sequence Charts
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Message-passing automata are expressively equivalent to EMSO logic
Theoretical Computer Science - Concurrency theory (CONCUR 2004)
A theory of regular MSC languages
Information and Computation
A Kleene theorem and model checking algorithms for existentially bounded communicating automata
Information and Computation
Matching scenarios with timing constraints
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Communicating timed automata: the more synchronous, the more difficult to verify
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Efficient scenario verification for hybrid automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A concurrency-preserving translation from time Petri nets to networks of timed automata
Formal Methods in System Design
Symbolically bounding the drift in time-constrained MSC graphs
ICTAC'12 Proceedings of the 9th international conference on Theoretical Aspects of Computing
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
Reachability of communicating timed processes
FOSSACS'13 Proceedings of the 16th international conference on Foundations of Software Science and Computation Structures
Event clock message passing automata: a logical characterization and an emptiness checking algorithm
Formal Methods in System Design
| Hi-index | 0.00 |
We provide a framework for distributed systems that impose timing constraints on their executions. We propose a timed model of communicating finite-state machines, which communicate by exchanging messages through channels and use event clocks to generate collections of timed message sequence charts (T-MSCs). As a specification language, we propose a monadic secondorder logic equipped with timing predicates and interpreted over T-MSCs. We establish expressive equivalence of our automata and logic. Moreover, we prove that, for (existentially) bounded channels, emptiness and satisfiability are decidable for our automata and logic.