PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
The Vision of Autonomic Computing
Computer
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices
HICSS '05 Proceedings of the Proceedings of the 38th Annual Hawaii International Conference on System Sciences - Volume 09
The AMIDAR Class of Reconfigurable Processors
The Journal of Supercomputing
Hardware Based Online Profiling in AMIDAR Processors
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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In this contribution we present a novel general model for adaptive processors with organic features. We describe its basic principle of operation. The adaptive operations that are possible with this model are thoroughly discussed with respect to organic computing. The model allows runtime variations of the type and number of functional units as well as variations of the communication structure. Experimental results show that a processor implementing this model can self-optimize its architecture for several diverse applications.