PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Hardware Based Online Profiling in AMIDAR Processors
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
The organic features of the AMIDAR class of processors
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
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In this contribution we present a novel general model for adaptive processors. We describe its basic principle of operation and introduce several formal characterizations. The adaptive operations that are possible with this model are thoroughly discussed. The model allows runtime variations of the type and number of functional units as well as variations of the communication structure. We introduce simple heuristics to achieve adaptivity of the architecture. Experimental results show that a processor implementing this model can adapt its architecture to the requirements of diverse applications.