PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices
HICSS '05 Proceedings of the Proceedings of the 38th Annual Hawaii International Conference on System Sciences - Volume 09
The AMIDAR Class of Reconfigurable Processors
The Journal of Supercomputing
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
The organic features of the AMIDAR class of processors
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
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Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. Yet, the question has to be answered, which parts of the running application should be transformed into hardware. The migration of complete methods or procedures into hardware is often not feasible. In this contribution we show a hardware circuit that enables the processor to collect an execution profile of Java methods with a high resolution. We also show, how this profile information can be used to make reasonable choices for candidate instruction sequences.