VLSI Architectures for High-Speed Range Estimation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Stereo Correspondence with Compact Windows via Minimum Ratio Cycle
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Parallel Real Time Implementation of Stereo Matching
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Towards real-time stereo employing parallel algorithms for edge-based and dense stereo matching
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
A Stereo Machine for Video-Rate Dense Depth Mapping and Its New Applications
CVPR '96 Proceedings of the 1996 Conference on Computer Vision and Pattern Recognition (CVPR '96)
Tyzx DeepSea High Speed Stereo Vision System
CVPRW '04 Proceedings of the 2004 Conference on Computer Vision and Pattern Recognition Workshop (CVPRW'04) Volume 3 - Volume 03
Video-rate stereo depth measurement on programmable hardware
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Computer Vision and Image Understanding
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This paper describes a real-time stereo depth measurement image processing system. This system uses Xilinx Virtex-II Series XC2V3000 FPGA and generates 8-bit sub-pixel disparities on 640 by 480 resolution images at video rate (60 frames/sec) with maximum disparity ranges of up to 128 pixels. The implemented stereo matching algorithm finds a minimum of window-based sum of absolute difference (SAD) operation. And the preprocessing, scale transformation and final stage compensation technique are adopted for maximizing the wide disparity range detection. The proposed vision system is suitable for real-time range estimation and robot navigation applications.