Exploiting a new level of DLP in multimedia applications
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Design and test space exploration of transport-triggered architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
IEEE Micro
A Two Dimensional Vector Architecture for Multimedia
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Superword-Level Parallelism in the Presence of Control Flow
Proceedings of the international symposium on Code generation and optimization
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SIMD architectures are ubiquitous in general purpose and embedded processors to achieve future multimedia performance goals However, limited to on chip resources and off-chip memory bandwidth, current SIMD extension only works on short sets of SIMD elements This leads to large parallelization overhead for small loops in multimedia applications such as loop handling and address generation This paper presents SIMD-Vector (SV) architecture to enhance SIMD parallelism exploration It attempts to gain the benefits of both SIMD instructions and more traditional vector instructions which work on numerous values Several instructions are extended that allows the programmer to work on large vectors of data and those large vectors are executed on a smaller SIMD hardware by a loop controller To preserve the register file size for holding much longer vectors, we introduce a technique that the long vector references are performed on only one SIMD register in many iterations We provide a detailed description of the SV architecture and its comparison with traditional vector architecture We also present a quantitative analysis of the dynamic instruction size decrease and performance improvement of SV architecture.