DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Predicting interconnect delay for physical synthesis in a FPGA CAD flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.