Modelling systemc process behavior by the UML method state machines

Authors:
Elvinia Riccobene;Patrizia Scandurra
Affiliations:
Dipartimento di Matematica e Informatica, Università di Catania, Catania, Italy;Dipartimento di Matematica e Informatica, Università di Catania, Catania, Italy
Venue:
RISE'04 Proceedings of the First international conference on Rapid Integration of Software Engineering Techniques
Year:
2004

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Abstract

We describe the SystemC Process State Machines that we have defined, as a variation of the UML method state machines, to model the behavior of reactive processes of the SystemC language. They are part of a complete UML 2.0 profile for SystemC that we have developed to improve the SoC (System on a Chip) design flow in order to provide a modelling framework which allows high-level designing SoC components in the style of UML using the SystemC design primitives.