Embedded UML: a merger of real-time UML and co-design
Proceedings of the ninth international symposium on Hardware/software codesign
System Design with SystemC
System-on-chip validation using UML and CWL
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Model-Driven SoC Design via Executable UML to SystemC
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modelling systemc process behavior by the UML method state machines
RISE'04 Proceedings of the First international conference on Rapid Integration of Software Engineering Techniques
A Scenario-Based Validation Language for ASMs
ABZ '08 Proceedings of the 1st international conference on Abstract State Machines, B and Z
SystemC/C-based model-driven design for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A Model-Driven Design Framework for Massively Parallel Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
Rigorous Methods for Software Construction and Analysis
Principles for the realization of an open simulation framework based on fUML (WIP)
Proceedings of the Symposium on Theory of Modeling & Simulation - DEVS Integrative M&S Symposium
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.00 |
In this paper we present a UML 2.0 profile for the SystemC language, which is a consistent set of modeling constructs designed to lift both structural and behavioral features (including events and time features) of the SystemC language to UML level. The main target of this profile is to provide a means for software and hardware engineers to improve the current industrial Systems-on-a-Chip (SoC) design methodology joining the capabilities of UML and SystemC to operate at system-level.