An Experience Using Two Covert Channel Analysis Techniques on a Real System Design
IEEE Transactions on Software Engineering - Special issue on computer security and privacy
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ACM Transactions on Computer Systems (TOCS)
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Communications of the ACM
SP '94 Proceedings of the 1994 IEEE Symposium on Security and Privacy
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ICDCSW '05 Proceedings of the Second International Workshop on Security in Distributed Computing Systems (SDCS) (ICDCSW'05) - Volume 02
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SP'96 Proceedings of the 1996 IEEE conference on Security and privacy
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FAST'06 Proceedings of the 4th international conference on Formal aspects in security and trust
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Computer Networks: The International Journal of Computer and Telecommunications Networking
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In this paper, we examine general mechanisms that a covert channel may exploit and derive new minimum requirements for setting up a covert channel. We also propose a new classification of covert channels based on our analysis. Unlike the non-interference approaches, our approach is constructive, allowing the direct examination of system architectures at different abstraction levels for the presence or absence of the mechanisms that can be exploited to create covert channels. Also, unlike past research on covert channel capacity estimation which employed a synchronous channel model, we point out that covert channels are generally non-synchronous. To capture the asynchronous nature of covert channels, we propose the deletion-insertion channel model as a more general basis for covert channel capacity estimation. This enables modeling the effects of system behavior on covert channel capacity, leading to a more accurate upper bound of the resulting channel capacity.