Real-Time Video Compression: Techniques and Algorithms
Real-Time Video Compression: Techniques and Algorithms
3D-DCT Quantization as a Compression Technique for Video Sequences
VSMM '97 Proceedings of the 1997 International Conference on Virtual Systems and MultiMedia
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
Low-complexity multiple description coding of video based on 3D block transforms
EURASIP Journal on Embedded Systems
EURASIP Journal on Applied Signal Processing
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
IEEE Transactions on Computers
Three-Dimensional Transforms and Entropy Coders for a Fast Embedded Color Video Codec
SIBGRAPI '08 Proceedings of the 2008 XXI Brazilian Symposium on Computer Graphics and Image Processing
Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers
Microprocessors & Microsystems
Distributions of 3D DCT coefficients for video
ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
New low complexity DCT based video compression method
ICT'09 Proceedings of the 16th international conference on Telecommunications
An adaptive 3-D discrete cosine transform coder for medical image compression
IEEE Transactions on Information Technology in Biomedicine
Dynamic control of motion estimation search parameters for low complex H.264 video coding
IEEE Transactions on Consumer Electronics
Hardware architecture design of video compression for multimedia communication systems
IEEE Communications Magazine
Variable temporal-length 3-D discrete cosine transform coding
IEEE Transactions on Image Processing
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The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art.