Minimizing power in hardware/software partitioning

Authors:
Jigang Wu;Thambipillai Srikanthan;Chengbin Yan
Affiliations:
Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

Citing 8
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Abstract

Power efficiency is one of the major considerations in the current hardware/software co-designs. This paper models hardware/ software partitioning as an optimization problem with the objective of minimizing power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the idea of solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution in $O(n.\mathcal{A}.\mathcal{E})$ for n code fragments under the constraints: hardware area $\mathcal{A}$ and execution time $\mathcal{E}$. Computational results show that the approximate solution produced by the proposed heuristic algorithm is nearly optimal in comparison to the optimal solution produced by the proposed exact algorithm.