Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
IEEE Transactions on Computers
Architectural support for copy and tamper resistant software
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Authenticated Encryption: Relations among Notions and Analysis of the Generic Composition Paradigm
ASIACRYPT '00 Proceedings of the 6th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
AEGIS: architecture for tamper-evident and tamper-resistant processing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Caches and Hash Trees for Efficient Memory Integrity Verification
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Efficient Memory Integrity Verification and Encryption for Secure Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
Proceedings of the 43rd annual Design Automation Conference
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This paper presents a comparison of two engines providing encryption and authentication of data exchanged between a System on Chip (SoC) and its external memory. The first engine is based on a generic composition scheme, meaning that each required security service, confidentiality and authentication, is guaranteed by a dedicated algorithm i.e. respectively AES (Advanced Encryption Standard) and CBC-MAC (Message Authentication Code). The second one, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), uses AES encryption to provide both properties to data by adding the authentication capability to block cipher. Performance evaluations show that our scheme PE-ICE always outperforms the combination of AES encryption and CBC-MAC.