Simulation of LET models in simulink and ptolemy

  • Authors:
  • Patricia Derler;Andreas Naderlinger;Wolfgang Pree;Stefan Resmerita;Josef Templ

  • Affiliations:
  • C. Doppler Laboratory Embedded Software Systems, University of Salzburg;C. Doppler Laboratory Embedded Software Systems, University of Salzburg;C. Doppler Laboratory Embedded Software Systems, University of Salzburg;C. Doppler Laboratory Embedded Software Systems, University of Salzburg;C. Doppler Laboratory Embedded Software Systems, University of Salzburg

  • Venue:
  • Monterey'08 Proceedings of the 15th Monterey conference on Foundations of Computer Software: future Trends and Techniques for Development
  • Year:
  • 2008

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Abstract

This paper describes two different approaches of simulating embedded control software whose real-time requirements are explicitly specified by means of the Logical Execution Time (LET) abstraction introduced in the Giotto project. As simulation environments we chose the black-box MATLAB/Simulink product and the open-source project Ptolemy II. The paper first sketches the modeling of LET-based components with the Timing Definition Language (TDL). As the LET abstraction allows the platform-independent modeling of the timing behavior of embedded software, a correct simulation of TDL components is equivalent to the behavior on a specific platform. We integrated TDL with both MATLAB/Simulink and Ptolemy and highlight the differences and similarities of the particular TDL simulation.