IOMMU: strategies for mitigating the IOTLB bottleneck

Authors:
Nadav Amit;Muli Ben-Yehuda;Ben-Ami Yassour
Affiliations:
Technion, Israel Institute of Technology, Haifa, Israel;IBM R&D Labs in Israel, Haifa, Israel;IBM R&D Labs in Israel, Haifa, Israel
Venue:
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Year:
2010

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Abstract

The input/output memory management unit (IOMMU) was recently introduced into mainstream computer architecture when both Intel and AMD added IOMMUs to their chip-sets. An IOMMU provides memory protection from I/O devices by enabling system software to control which areas of physical memory an I/O device may access. However, this protection incurs additional direct memory access (DMA) overhead due to the required address resolution and validation. IOMMUs include an input/output translation lookaside buffer (IOTLB) to speed-up address resolution, but still every IOTLB cache-miss causes a substantial increase in DMA latency and performance degradation of DMA-intensive workloads. In this paper we first demonstrate the potential negative impact of IOTLB cache-misses on workload performance. We then propose both system software and hardware enhancements to reduce IOTLB miss rate and accelerate address resolution. These enhancements can lead to a reduction of over 60% in IOTLB miss-rate for common I/O intensive workloads.