Scalable distributed visualization using off-the-shelf components
PVGS '99 Proceedings of the 1999 IEEE symposium on Parallel visualization and graphics
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Designing Run-Time Reconfigurable Systems with JHDL
Journal of VLSI Signal Processing Systems
Sepia: Scalable 3D Compositing Using PCI Pamette
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
High-Visibility Debug-By-Design for FPGA Platforms
The Journal of Supercomputing
Applications of adaptive computing systems for signal processing challenges
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Motivating future interconnects: a differential measurement analysis of PCI latency
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IOMMU: strategies for mitigating the IOTLB bottleneck
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
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We describe the use of a reconfigurable board to obtain information on the performance that can be expected on particular systems. Our goal is to use the reconfigurability, of the board's interface to test a system and discover not only the maximum bandwidth and best latency attainable, but also the way to reliably achieve these figures. The board we present uses the now widespread PCI bus. PCI is sufficiently complex, and its implementations sufficiently varied, that it is impossible to guess the performance that can be obtained by a specific board on a specific computer with the only technical characteristics of the two in hand. We observe astonishing performance differences between almost identical systems and comparable figures between small PCs and big servers. Our performance tests can be an end in themselves, however, they also serve to demonstrate the value of a reconfigurable bus interface. With the same board, we can test and choose a system, make informed architectural decisions on the hardware/software interface, and then finely tune the bus interface to get maximum and predictable figures in the running application.