Digital design principles and practices
Digital design principles and practices
Evaluation of spoken language systems: the ATIS domain
HLT '90 Proceedings of the workshop on Speech and Natural Language
Statistical methods for speech recognition
Statistical methods for speech recognition
Contemporary Logic Design
VHDL Designer's Reference
Systems performance measurement on PCI Pamette
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Hidden Markov modeling and fuzzy controllers in FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
An integrated circuit based speech-recognition system
An integrated circuit based speech-recognition system
Pen and speech recognition in the user interface for mobile multimedia terminals
Pen and speech recognition in the user interface for mobile multimedia terminals
Efficient speech recognition using subvector quantization and discrete-mixture HMMs
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 02
Quantization of cepstral parameters for speech recognition over the World Wide Web
IEEE Journal on Selected Areas in Communications
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
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An architecture is presented for real-time continuousspeech recognition based on a modified hidden Markov model. Thealgorithm is adapted to the needs of continuous speech recognition byefficient encoding of the state space, and logarithmic encoding ofthe weights so that products can be computed as sums. The paperpresents the algorithm and its application related modifications, themapping of the algorithm to a special purpose architecture, and thedetailed design of this architecture using configurable logic.Emphasis is given on how the attributes of the algorithm areexploited in a configurable logic based design. A concrete designexample is presented with a coprocessor engine having one large FPGA,64 Mbytes of synchronous DRAM (SDRAM), a small FPGA as a SDRAMcontroller, and 2 Mbytes SRAM. This engine operating at 66 MHzperforms roughly nine times as fast as a high end personal computerrunning a fully optimized version of the same algorithm.