Speech Communication - Special issue on interactive voice technology for telecommunication applications (IVITA '96)
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Speech recognition chip for monosyllables
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Speech Synthesis and Recognition
Speech Synthesis and Recognition
Reconfigurable Computing for Speech Recognition: Preliminary Findings
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Speech interface VLSI for car applications
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 01
A single chip phoneme based HMM speech recognition system for consumer applications
IEEE Transactions on Consumer Electronics
Single-chip speech recognition system based on 8051 microcontroller core
IEEE Transactions on Consumer Electronics
Hardware speech recognition for user interfaces in low cost, low power devices
Proceedings of the 42nd annual Design Automation Conference
An implementation of an FPGA-based embedded gesture recognizer using a data glove
Proceedings of the 2nd international conference on Ubiquitous information management and communication
FPGA implementation for GMM-based speaker identification
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
A GMM-based speaker identification system on FPGA
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. Any device that can reduce the load on, for example, a PC's processor, is advantageous. Hence we present FPGA implementations of the decoder based alternately on discrete and continuous hidden Markov models (HMMs) representing monophones, and demonstrate that the discrete version can process speech nearly 5,000 times real time, using just 12% of the slices of a Xilinx Virtex XCV1000, but with a lower recognition rate than the continuous implementation, which is 75 times faster than real time, and occupies 45% of the same device.