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A Sorting Classification of Parallel Rendering
IEEE Computer Graphics and Applications
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
InfiniteReality: a real-time graphics system
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Parallel Computing - Special issue on applications: parallel graphics and visualisation
A Competitive Analysis of Load Balancing Strategiesfor Parallel Ray Tracing
The Journal of Supercomputing
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IEEE Computational Science & Engineering
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EGPGV '02 Proceedings of the Fourth Eurographics Workshop on Parallel Graphics and Visualization
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EGPGV '02 Proceedings of the Fourth Eurographics Workshop on Parallel Graphics and Visualization
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EGPGV '02 Proceedings of the Fourth Eurographics Workshop on Parallel Graphics and Visualization
Next-generation visual supercomputing using PC clusters with volume graphics hardware devices
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
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IEEE Computer Graphics and Applications
Distributed rendering of interactive soft shadows
Parallel Computing - Parallel graphics and visualisation
Out-of-core sort-first parallel rendering for cluster-based tiled displays
Parallel Computing - Parallel graphics and visualisation
Sort-First, Distributed Memory Parallel Visualization and Rendering
PVG '03 Proceedings of the 2003 IEEE Symposium on Parallel and Large-Data Visualization and Graphics
Interactive parallel visualization of large particle datasets
Parallel Computing - Parallel graphics and visualization
Scalable isosurface visualization of massive datasets on commodity off-the-shelf clusters
Journal of Parallel and Distributed Computing
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HCIV'09 Proceedings of the Second IFIP WG 13.7 conference on Human-computer interaction and visualization
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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Interactive parallel visualization of large particle datasets
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This paper describes a visualization architecture for scalable computer systems. The architecture is currently being prototyped for use in Beowulf-class clustered systems. A set of OpenGL frame buffers are driven in parallel by a set of CPUs. The visualization architecture merges the contents of these frame buffers by user-programmable associative and commulative combining operations. The system hardware is built from off-the-shelf components including OpenGL accelerators, Field Programmable Gate Arrays (FPGAs), and gigabit network interfaces and switches. A second-generation prototype supports 60 Hz operation at 1024 × 1024 pixel resolution with interactive latency up to 1000 nodes.