Performance analysis of error-correcting binary decision diagrams

Authors:
Helena Astola;Stanislav Stankovi$#263/;Jaakko T. Astola
Affiliations:
Dept. of Signal Processing, Tampere University of Technology, Tampere, Finland;Dept. of Signal Processing, Tampere University of Technology, Tampere, Finland;Dept. of Signal Processing, Tampere University of Technology, Tampere, Finland
Venue:
EUROCAST'11 Proceedings of the 13th international conference on Computer Aided Systems Theory - Volume Part II
Year:
2011

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Abstract

Decision diagrams are an efficient way of representing switching functions and they are easily mapped to technology. A layout of a circuit is directly determined by the shape and the complexity of the decision diagram. By combining the theory of error-correcting codes with decision diagrams, it is possible to form robust circuit layouts, which can detect and correct errors. The method of constructing robust decision diagrams is analogous to the decoding process of linear codes, and is based on simple matrix and look-up operations. In this paper, the performance of robust binary decision diagrams is analyzed by determining the error probabilities for such constructions. Depending on the error-correcting properties of the code used in the construction, the error probability of a circuit can be significantly decreased by a robust decision diagram.