An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Energy optimization techniques in cluster interconnects
Proceedings of the 2003 international symposium on Low power electronics and design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
A variable frequency link for a power-aware network-on-chip (NoC)
Integration, the VLSI Journal
Power reduction through physical placement of asynchronous routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A vertical bubble flow network using inductive-coupling for 3-D CMPs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Low-power techniques are proposed for the wireless three-dimensional Network-on-Chips (wireless 3-D NoCs), in which routers on the same chip are connected with metal wires while those on the different chips are connected wirelessly using the inductive-coupling. For saving power consumption of the vertical link, the clock and power supplies to the transmitter are stopped when their utilizations are between a specified range. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold. In order to keep performance, on-demand activation is used in this paper. As long as flit comes, the dormant data transmitter or the whole vertical link will be activated immediately without any judgement. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 23.4%-29.3%, while the performance overhead is less than 2.4%.