A guided tour of Chernoff bounds
Information Processing Letters
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
An Implementation of DES and AES, Secure against Some Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Simplified Adaptive Multiplicative Masking for AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Enhanced Correlation Power Analysis Attack on Smart Card
ICYCS '08 Proceedings of the 2008 The 9th International Conference for Young Computer Scientists
Enhanced Correlation Power Analysis Using Key Screening Technique
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
Ways to enhance differential power analysis
ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
A side-channel analysis resistant description of the AES s-box
FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
A proposition for correlation power analysis enhancement
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A stochastic model for differential side channel cryptanalysis
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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The paper presents an enhancement of univariate Differential Power Analysis (DPA), referred to as Probable Key Differential Power Analysis (PKDPA) . The proposed analysis uses the standard Difference of Means (DoM) test as the distinguisher and employs its enhancement strategy to reduce the number of power traces required to mount the attack. Theoretical analysis for the developed attack has been furnished to justify the efficiency of the proposed attack in retrieving the key using significantly less number of traces compared to conventional DPA attacks. The theoretical claims have been supported by extensive experiments on real life attacks mounted on Field Programmable Gate Array (FPGA) implementations of the Data Encryption Standard (DES), Triple-DES (3-DES) and the Advanced Encryption Standard (AES). The efficacy of the proposed method is further proved by attacking a masked implementation of AES using only 13,000 power traces.