Dynamically heterogeneous cores through 3D resource pooling

Authors:
Houman Homayoun;Vasileios Kontorinis;Amirali Shayan;Ta-Wei Lin;Dean M. Tullsen
Affiliations:
University of California San Diego;University of California San Diego;University of California San Diego;University of California San Diego;University of California San Diego
Venue:
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Year:
2012

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Abstract

This paper describes an architecture for a dynamically heterogeneous processor architecture leveraging 3D stacking technology. Unlike prior work in the 2D plane, the extra dimension makes it possible to share resources at a fine granularity between vertically stacked cores. As a result, each core can grow or shrink resources, as needed by the code running on the core. This architecture, therefore, enables runtime customization of cores at a fine granularity and enables efficient execution at both high and low levels of thread parallelism. This architecture achieves performance gains from 9 -- 41%, depending on the number of executing threads, and gains significant advantage in energy efficiency of up to 43%.