Multigrid-like technique for power grid analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
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A link breaking methodology is introduced to reduce voltage degradation within mesh structured power distribution networks. The resulting power distribution network combines a single power distribution network to lower the network impedance, and multiple networks to reduce noise coupling among the circuits. Since the sensitivity to supply voltage variations within a power distribution network can vary among different circuits, the proposed methodology reduces the voltage drop at the more sensitive circuits, while penalizes the less sensitive circuits. The proposed methodology is evaluated for two case studies, demonstrating a reduction in the voltage drop in sensitive circuits. Based on these case studies, the voltage is improved by, on average, 4% at those nodes with the highest sensitivity. The voltage after application of the link breaking methodology is, on average, 96% of the ideal power supply voltage. Lowering the noise on the power network enhances, on average, the maximum operating frequency by 11% by utilizing the proposed link breaking methodology.