A limits study of benefits from nanostore-based future data-centric system architectures

  • Authors:

  • Jichuan Chang;Parthasarathy Ranganathan;Trevor Mudge;David Roberts;Mehul A. Shah;Kevin T. Lim

  • Affiliations:

  • HP Labs, Palo Alto, CA, USA;HP Labs, Palo Alto, CA, USA;University of Michigan, Ann Arbor, MI, USA;Micron, Ann Arbor, MI, USA;Nou Data, Palo Alto, CA, USA;HP Labs, Palo Alto, CA, USA

  • Venue:
  • Proceedings of the 9th conference on Computing Frontiers
  • Year:
  • 2012

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Abstract

The adoption of non-volatile memories (NVMs) in system architecture and the growth in data-centric workloads offer exciting opportunities for new designs. In this paper, we examine the potential and limit of designs that move compute in close proximity to NVM-based data stores. To address the challenges in evaluating such system architectures for distributed systems, we develop and validate a new methodology for large-scale data-centric workloads. We then study "nanostores" as an example design that constructs distributed systems from building blocks with 3D-stacked compute and NVM layers on the same chip, replacing both traditional storage and memory with NVM. Our limits study demonstrates significant potential of this approach (3-162X improvement in energy delay product) over 2015 baselines, particularly for IO-intensive workloads. We also discuss and quantify the impact of network bandwidth, software scalability, and power density, and design tradeoffs for future NVM-based data-centric architectures.