CoreSymphony architecture

Authors:
Tomoyuki Nagatsuka;Yoshito Sakaguchi;Kenji Kise
Affiliations:
Tokyo Institute of Technology, Tokyo, Japan;Tokyo Institute of Technology, Tokyo, Japan;Tokyo Institute of Technology, Tokyo, Japan
Venue:
Proceedings of the 9th conference on Computing Frontiers
Year:
2012

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Abstract

We propose CoreSymphony architecture, which aims at balancing single-thread performance and multi-thread performance on CMPs. The former version of CoreSymphony had complex branch predictor, re-order buffer, and in-order state management mechanism. In this paper, we solve these problems and evaluate the performance of CoreSymphony.