CoreSymphony: an efficient reconfigurable multi-core architecture

Authors:
Tomoyuki Nagatsuka;Yoshito Sakaguchi;Takayuki Matsumura;Kenji Kise
Affiliations:
Tokyo Institute of Technology, Japan;Tokyo Institute of Technology, Japan;Tokyo Institute of Technology, Japan;Tokyo Institute of Technology, Japan
Venue:
ACM SIGARCH Computer Architecture News
Year:
2011

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Abstract

This paper describes CoreSymphony, a cooperative and reconfigurable superscalar processor architecture that improves single-thread performance in chip multiprocessor. CoreSymphony enables some narrow-issue cores to be fused into a single wide-issue core. In this paper, we describe the problems associated with achieving the cooperative superscalar processor. We then describe techniques by which to overcome these problems. The evaluation results obtained using SPEC2006 benchmarks indicate that four-core fusion achieves 88% higher IPC than an individual core.