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While it has long been argued that near-threshold (~0.5V) operation of CMOS technologies can dramatically improve power efficiency, widespread application of such low voltage operation to VLSI systems has yet to materialize. This is due in part to practical system workload demands, in which single-thread performance needs can limit strategies to improve parallelizeable throughput performance, but also due to barriers in the ability of supporting hardware to counter variability and reliability concerns while maintaining power efficiency throughout the system. This paper describes the issues on which the realization of near-threshold computing depends to explain why this strategy is not yet pervasive today. However, recent advancements across the spectrum of system design--including heterogeneous architectures, transistor and memory technologies, power delivery, packaging, and I/O--suggest that as the market for throughput performance grows, hardware technologies may soon become available to practically harness the promise of near-threshold operation.