Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Authors:
Gerhard Schrom;Peter Hazucha;Jae-Hong Hahn;Volkan Kursun;Donald Gardner;Siva Narendra;Tanay Karnik;Vivek De
Affiliations:
Intel, Hillsboro, OR;Intel, Hillsboro, OR;Intel, Hillsboro, OR;University of Rochester, NY;Intel, Hillsboro, OR;Intel, Hillsboro, OR;Intel, Hillsboro, OR;Intel, Hillsboro, OR
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

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Abstract

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.