Fundamentals of Data Structures in C++
Fundamentals of Data Structures in C++
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
A pipelined memory architecture for high throughput network processors
Proceedings of the 30th annual international symposium on Computer architecture
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Shape Shifting Tries for Faster IP Route Lookup
ICNP '05 Proceedings of the 13TH IEEE International Conference on Network Protocols
Succinct representation of static packet classifiers
IEEE/ACM Transactions on Networking (TON)
The synergy between power-aware memory systems and processor voltage scaling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based scheme, we implement a set-ssociative SRAM based cache. We use two different algorithms, tree bitmap (TBM) and shape shifting trie (SST), to organize an IP routing table as a supernode tree composed of a group of supernodes. We add a small supernode cache in-between the processor and the low-level memory containing the IP routing table in a tree structure. The supernode cache stores recently visited supernodes of the longest matched prefixes in the IP routing tree. A supernode hitting in the cache reduces the number of accesses to the low-level memory, leading to a fast IP lookup. According to our simulations, up to 72% memory accesses can be avoided by a 128KB TBM supernode cache for the selected three trace files, and up to 78% memory accesses can be reduced while using a same size of SST supernode cache. Average TBM and SST supernode cache miss ratios are as low as 4% and 7%, respectively. Compared to a TCAM with the same size, the TBM and SST supernode caches can both reduce 77% of energy consumption.