Fair Scheduling in Internet Routers
IEEE Transactions on Computers
FPCF Input-Queued Packet Switch for Variable-Size Packets
ICN '01 Proceedings of the First International Conference on Networking-Part 2
MMR: A MultiMedia Router architecture to support hybrid workloads
Journal of Parallel and Distributed Computing
Input register architectures of high speed router for supporting the PHB of differentiated services
QoS-IP'05 Proceedings of the Third international conference on Quality of Service in Multiservice IP Networks
Input queued switches for variable length packets: analysis for Poisson and self-similar traffic
Computer Communications
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While the Internet has quietly served as a research and education vehicle for more than two decades, the last few years have witnessed its tremendous growth and its great potential for providing a wide variety of services. As a result, input-queued switching architectures, because of their distinguished advantage in building scalable switches, are currently receiving a lot of attention from both academia and industry as an attractive alternative for developing future-generation ATM/IP switches/routers. However, the problem of designing scheduling algorithms with QoS guarantees for input-queued switches has always been known to be a very challenging problem. We give an overview of the efforts in designing scheduling algorithms capable of providing QoS guarantees for input-queued switches. These algorithms are classified under three categories: those based on slot time assignment, those based on maximal matching, and those based on stable matching. We also present some open problems on this topic as future research directions in this area.