A New Synthesis of Symmetric Functions
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Symmetry detection for incompletely specified functions
Proceedings of the 41st annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Testable design of digital summation threshold logic array for synthesis of symmetric functions
International Journal of Computers and Applications
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A new technique of synthesizing totally symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circuits. Nonconsecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results shows that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn, reduces testing time, as compared to those of the best-known earlier methods