Testable design of digital summation threshold logic array for synthesis of symmetric functions

Authors:
H. Rahaman;D. K. Das;B. B. Bhattacharya
Affiliations:
Bengal Engineering and Science University, Shibpur, Howrah, India;Jadavpur University, Calcutta, India;Indian Statistical Institute, Calcutta, India
Venue:
International Journal of Computers and Applications
Year:
2007

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Abstract

A new cellular array is introduced for synthesizing totally symmetric Boolean functions. The cellular structure uses only 3-input, 3-output AND--OR cells, and is fully path-delay fault testable. It is an improved version of the classical digital summation threshold logic array used earlier in logic design [1]. It admits a universal test set of length 2n that detects all single stuck-at faults, where n is the number of input variables. The proposed design is useful in view of the fact that two-level realizations of most of the symmetric functions are known to be path-delay untestable. Experiments on several circuits demonstrate that the structure offers less area and fewer number of paths compared to earlier delay testable proposals.